Add_half_structural

這禮拜老師教的，讓我受益很多，對於verilog的這門課，開始有了更濃厚的興趣，使用程式上，也有著很大的進步。寫verilog時，一定要按步驟走，先把基礎打好，這樣以後才能更靈活的運用它！
==================================================================

module top;
reg a,b;
wire sum,c_out;
Add_half_structural m1(sum,c_out,a,b);
initial
begin
a=0;
b=0;
#2000 $finish;
end
always
#100 a=~a;
always
#50 b=~b;
endmodule

module Add_half_structural(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xorf201 G1(sum,a,b);
nandf201 G2(c_out_bar, a,b);
invf101 G3(c_out,c_out_bar);
endmodule

module nandf201(O,A1,B1);
input A1,B1;
output O;
nand(O,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.50:7.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
(B1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module xorf201(O,A1,B1);
input A1,B1;
output O;
xor(O,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.50:7.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
(B1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module invf101(O,A1);
input A1;
output O;
not(O,A1);
specify
specparam
Tpd_0_1=1.53:4.09:6.75,
Tpd_1_0=0.53:4.50:6.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule