Nand_Latch simulation之心得

今天老師教的東西，有些不太懂，所給的作業(88頁的)有一個做不出來，完全照著課本打，但總覺得好像怪怪的，一直跑不出想要的圖形，改天自己一定要好好鑽研一下，使之充實自我，不白費光陰！

Nand_Latch simulation with delay

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;
Nand_Latch_1 M1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear=%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0; clear=1;
#10 preset=1;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end
initial
#60 $finish;
endmodule
module Nand_Latch_1(q,qbar,preset,clear);
input preset,clear;
output q,qbar;
nand #1 g1(q,preset,qbar);
nand #1 g2(qbar,clear,q);
endmodule

Nand_Latch_1

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;
Nand_Latch_1 M1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear=%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0; clear=1;
#10 preset=1;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end
initial
#60 $finish;
endmodule
module Nand_Latch_1(q,qbar,preset,clear);
input preset,clear;
output q,qbar;
nand g1(q,preset,qbar),
g2(qbar,clear,q);
endmodule

Data structures and event propagation delay

今天老師教delay，讓我覺得蠻實用的，很多的電路都會用當delay這個地方！在作的過程中，不知道要怎麼把訊息c顯示出來，後來想一想才知道用兩個副程式寫就好了！
==================================================================

module top;
reg a,b;
wire c,d;
event_driven m1(c,a,b);
no m1(d,c);
initial
begin
a=1;
b=0;
#2000 $finish;
end
always #30 a=~a;
always #20 b=~b;
endmodule

module event_driven(c,a,b);
input a,b;
output c;
and #3(c,a,b);
endmodule
module no(d,c);
input c;
output d;
not #2(d,c);
endmodule

2位元比較器之compare_2_algo

module top;
reg A,B;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_algo m1(A_lt_B,A_gt_B,A_eq_B,A,B);
initial
begin
A=0;
B=0;
#2000 $finish;
end
always #100 A=~A;
always #50 B=~B;
endmodule

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;

always @ (A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B)A_eq_B=1;
else if (A>B)A_gt_B=1;
else A_lt_B=1;
end
endmodule

2位元比較器之心得

這次上課，因為有分工合作的關係，一人打一個程式，然後再自己輸入訊號，感覺蠻有效率的，希望下次上課時，也都能像這次上課一樣順利！

2位元比較器之compare_2b

module top;
reg A1,A0,B1,B0;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2b m1(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
initial
begin
A1=0;
A0=0;
B1=0;
B0=0;

#2000 $finish;
end
always
#30 A1=~A1;
always
#40 A0=~A0;
always
#50 B1=~B1;
always
#60 B0=~B0;

endmodule

module compare_2b(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=({A1,A0}<{B1,B0}); assign A_gt_B=({A1,A0}>{B1,B0});
assign A_eq_B=({A1,A0}=={B1,B0});
endmodule

2位元比較器之compare_2a

module top;
reg A1,A0,B1,B0;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2a m1(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
initial
begin
A1=0;
A0=0;
B1=0;
B0=0;

#2000 $finish;
end
always
#30 A1=~A1;
always
#40 A0=~A0;
always
#50 B1=~B1;
always
#60 B0=~B0;

endmodule


module compare_2a(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(~A1)&amp;amp;(~A0)&B0(~A0)&B1&B0;
assign A_gt_B=A1&(~B1)A0&amp;amp;(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B=(~A1)&(~A0)&amp;amp;(~B1)&(~B0)(~A1)&A0&(~B1)&B0A1&A0&B1&B0A1&(~A0)&B1&(~B0);
endmodule

2位元比較器之compare_2_str

module top;
reg A1,A0,B1,B0;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_str m1(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
initial
begin
A1=0;
A0=0;
B1=0;
B0=0;

#2000 $finish;
end
always
#30 A1=~A1;
always
#40 A0=~A0;
always
#50 B1=~B1;
always
#60 B0=~B0;

endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;

or (A_lt_B,w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B0);
xnor (w5,A0,B0);
endmodule

16-bit ripple-carry adder

感覺這次教的比較難，用了好久才跑出來，若不是老師的教導，我想我應該也做不出來吧，難度提高的同時，當寫出來的成就感，是無法用言語形容的！
==================================================================

module top;
reg [15:0] a,b;
reg c_in;
wire [15:0] sum;
wire c_out;
Add_rca_16 m1(sum,c_out,a,b,c_in);
initial
begin
a=0;
b=0;
c_in=0;

#2000 $finish;
end
always
#100 a[0]=~a[0];
always
#150 b[1]=~b[1];
always
#200 c_in=~c_in;

endmodule

module Add_rca_16 (sum,c_out,a,b,c_in);
output [15:0] sum;
output c_out;
input [15:0] a,b;
input c_in;
wire c_in,c_in4,c_in8,c_in12,c_out;
Add_rca_4 M1(sum[3:0], c_in4, a[3:0], b[3:0], c_in);
Add_rca_4 M2(sum[7:4], c_in8, a[7:4], b[7:4], c_in4);
Add_rca_4 M3(sum[11:8], c_in12, a[11:8], b[11:8], c_in8);
Add_rca_4 M4(sum[15:12], c_out, a[15:12], b[15:12], c_in12);
endmodule

module Add_rca_4(sum,c_out,a,b,c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire c_in4,c_in3,c_in2;
Add_full G1 (sum[0],c_in2,a[0],b[0],c_in);
Add_full G2 (sum[1],c_in3,a[1],b[1],c_in2);
Add_full G3 (sum[2],c_in4,a[2],b[2],c_in3);
Add_full G4 (sum[3],c_out,a[3],b[3],c_in4);
endmodule

module Add_full(s,c_out,a,b,c_in);
output s,c_out;
input a,b,c_in;
wire s1,c1,c2,c_out_bar;
Add_half G1(s1,c1,a,b);
Add_half G2(s,c2,s1,c_in);
norf201 G3(c_out_bar,c1,c2);
invf101 G4(c_out,c_out_bar);
endmodule

module Add_half(s,c,a,b);
output s,c;
input a,b;
wire c_bar;
xorf201 G1(s,a,b);
nanf201 G2(c_bar,a,b);
invf101 G3(c,c_bar);
endmodule

module xorf201(O,A1,B1);
input A1,B1;
output O;
xor(O,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.50:7.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
(B1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module nanf201(O,A1,B1);
input A1,B1;
output O;
nand(O,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.50:7.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
(B1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module invf101(O,A1);
input A1;
output O;
not(O,A1);
specify
specparam
Tpd_0_1=1.53:4.09:6.75,
Tpd_1_0=0.53:4.50:6.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module norf201(O,A1,B1);
input A1,B1;
output O;
nor(O,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.50:7.34;
(A1=>O)=(Tpd_0_1,Tpd_1_0);
(B1=>O)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule