Verilog

Friday, May 12, 2006

2位元比較器之compare_2_algo

module top;
reg A,B;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_algo m1(A_lt_B,A_gt_B,A_eq_B,A,B);
initial
begin
A=0;
B=0;
#2000 $finish;
end
always #100 A=~A;
always #50 B=~B;
endmodule

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;

always @ (A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B)A_eq_B=1;
else if (A>B)A_gt_B=1;
else A_lt_B=1;
end
endmodule


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