test_Add_rca_4

感覺老師給的課堂作業比較難了，原本以為只是把課本的東西打一打，然後再加個top上去，就可以跑出來了，可是sum、c_out那邊都跑不出來。經由老師的開導，跟參考同學的程式碼，原來是要在內部加訊號就可，而不用加top送訊息進去，真是不經一事不長一智阿！
===================================================================
module test_Add_rca_4();
reg [3:0] a,b;
reg c_in;
wire [3:0] sum;
wire c_out;

initial
begin
a=1;
b=1;
c_in=1;
#40
$display ($time,,"sum=%b c_out=%b C_in4=%b c_in3=%b c_in2=%b c_in=%b",sum,c_out,M1.c_in4,M1.c_in3,M1.c_in2,c_in);
end

initial
begin
//stomulus patterns for data paths go here
end

Add_rca_4 M1 (sum,c_out,a,b,c_in); //module declaration
endmodule

module Add_rca_4(sum,c_out,a,b,c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire c_out,c_in4,c_in3,c_in2;
Add_full G1(sum[0],c_in2,a[0],b[0],c_in);
Add_full G2(sum[1],c_in3,a[1],b[1],c_in2);
Add_full G3(sum[2],c_in4,a[2],b[2],c_in3);
Add_full G4(sum[3],c_out,a[3],b[3],c_in4);

endmodule
module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;
half_adder m1(w1,w2,a,b);
half_adder m2(sum,w3,c_in,w1);
or (c_out,w2,w3);
endmodule

module half_adder(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule