Verilog

Friday, May 19, 2006

Data structures and event propagation delay

今天老師教delay,讓我覺得蠻實用的,很多的電路都會用當delay這個地方!在作的過程中,不知道要怎麼把訊息c顯示出來,後來想一想才知道用兩個副程式寫就好了!
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module top;
reg a,b;
wire c,d;
event_driven m1(c,a,b);
no m1(d,c);
initial
begin
a=1;
b=0;
#2000 $finish;
end
always #30 a=~a;
always #20 b=~b;
endmodule

module event_driven(c,a,b);
input a,b;
output c;
and #3(c,a,b);
endmodule
module no(d,c);
input c;
output d;
not #2(d,c);
endmodule

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